The present invention relates to microelectronic elements and their fabrication.
In the fabrication of microelectronic elements such as integrated circuits and other devices on semiconductor chips, trenches can be formed in a semiconductor substrate such as a wafer, which are then filled with a material. Subsequently, the material filling the trenches is recessed to a given depth below a major surface of the substrate. For example, in the fabrication of trench capacitors, it is common to fill trenches in the substrate with a polycrystalline semiconductor material such as polysilicon. Subsequently, the polysilicon within the trenches is recessed to a given depth below a major surface of the substrate.
Achieving a uniform recess depth when recessing the deposited polysilicon within trenches can be particularly challenging because of variations in height of existing material layers across the major surface of a wafer. Particularly, the thicknesses of the polysilicon and other deposited layers can vary substantially between the center of the wafer and the edge of the wafer. A substantial variation in topography between the center of the wafer and the edge before beginning to recess the deposited material can lead to significant non-uniform recess depth, even when uniform polysilicon deposition and etching processes are utilized. Conventional methods of processing involve process complexity, significant cost, and are subject to difficulties which can make defects difficult to manage within acceptable levels.
In light of the aforementioned difficulties of processes used to recess materials within trenches, it would be desirable to provide improved processes which allow a more uniform recess depth to be achieved despite topography of the substrate prior to beginning to recess the material.